Sense amplifier with split capacitors

ABSTRACT

Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.

CROSS REFERENCE

The present application for patent is a continuation of U.S. patentapplication Ser. No. 16/102,053 by Di Vincenzo et al., entitled “SenseAmplifier With Split Capacitors,” filed Aug. 13, 2018, assigned to theassignee hereof, and is expressly incorporated by reference in itsentirety herein.

BACKGROUND

The following relates generally to operating a memory array and morespecifically to techniques for reading a memory cell using a senseamplifier with split capacitors.

Memory devices are widely used to store information in variouselectronic devices such as computers, wireless communication devices,cameras, digital displays, and the like. Information is stored byprogramming different states of a memory device. For example, binarydevices have two states, often denoted by a logic “1” or a logic “0.” Inother systems, more than two states may be stored. To access the storedinformation, a component of the electronic device may read, or sense,the stored state in the memory device. To store information, a componentof the electronic device may write, or program, the state in the memorydevice.

Various types of memory devices exist, including magnetic hard disks,random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM),synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM(MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM),and others. Memory devices may be volatile or non-volatile. Non-volatilememory, e.g., FeRAM, may maintain their stored logic state for extendedperiods of time even in the absence of an external power source.Volatile memory devices, e.g., DRAM, may lose their stored state overtime unless they are periodically refreshed by an external power source.FeRAM may use similar device architectures as volatile memory but mayhave non-volatile properties due to the use of a ferroelectric capacitoras a storage device. FeRAM devices may thus have improved performancecompared to other non-volatile and volatile memory devices.

In general, memory devices may be improved by increasing memory celldensity, increasing read/write speeds, increasing reliability,increasing data retention, reducing power consumption, or reducingmanufacturing costs, among other metrics. In some cases, a readoperation of an FeRAM memory cell may include integrating a charge fromthe memory cell on an amplifier capacitor to determine a value stored onthe memory cell. The amplifier capacitor may, in some cases, be used foradditional purposes during the read operation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of a memory array that supports techniquesfor reading a memory cell using a sense amplifier with split capacitorsin accordance with aspects of the present disclosure.

FIG. 2 illustrates an example of a circuit that supports techniques forreading a memory cell using a sense amplifier with split capacitors inaccordance with aspects of the present disclosure.

FIG. 3 illustrates an example of hysteresis curves that supporttechniques for reading a memory cell using a sense amplifier with splitcapacitors in accordance with aspects of the present disclosure.

FIG. 4 illustrates an example of a circuit that supports techniques forreading a memory cell using a sense amplifier with split capacitors inaccordance with aspects of the present disclosure.

FIG. 5 illustrates an example of a timing diagram that supportstechniques for reading a memory cell using a sense amplifier with splitcapacitors in accordance with aspects of the present disclosure.

FIG. 6 illustrates an example of a timing diagram that supportstechniques for reading a memory cell using a sense amplifier with splitcapacitors in accordance with aspects of the present disclosure.

FIG. 7 illustrates an example of a timing diagram that supportstechniques for reading a memory cell using a sense amplifier with splitcapacitors in accordance with aspects of the present disclosure.

FIGS. 8A-8D illustrate examples of circuits that support techniques forreading a memory cell using a sense amplifier with split capacitors inaccordance with aspects of the present disclosure.

FIG. 9 illustrates an example of a circuit that supports techniques forreading a memory cell using a sense amplifier with split capacitors inaccordance with aspects of the present disclosure.

FIG. 10 illustrates an example of a circuit that supports techniques forreading a memory cell using a sense amplifier with split capacitors inaccordance with aspects of the present disclosure.

FIG. 11 illustrates a block diagram of a device that supports techniquesfor reading a memory cell using a sense amplifier with split capacitorsin accordance with aspects of the present disclosure.

FIGS. 12, 13, and 14 illustrate a method or methods for reading a memorycell using a sense amplifier with split capacitors in accordance withaspects of the present disclosure.

DETAILED DESCRIPTION

Ferroelectric memory cells include a capacitor that may store the valueof the memory cell. Reading the value of the memory cell may involvecoupling a digit line to the memory cell and transferring charge betweenthe memory cell capacitor and the digit line, and using a sensecomponent to “sense,” or determine, the value of the memory cell basedon the resulting voltage of the digit line.

The sense component of a ferroelectric memory device may include acapacitor, such as an amplifier capacitor, that may be used for sensingthe value of the cell. Electric charge may be transferred between theamplifier capacitor and the memory cell via the digit line during a readoperation. The amount of charge that is transferred between theamplifier capacitor and the memory cell may reflect the logic valuestored on the memory cell (e.g., whether the value is a “0” or a “1,”for example). The amplifier capacitor may be charged to an initial knownvoltage before the read operation, and the change in the amplifiercapacitor voltage during the read operation (due to the transferredelectric charge) may be used to sense the value of the memory cell. Thesense component may compare the voltage across the amplifier capacitor(which may serve as a proxy for the voltage on the digit line) with areference voltage to determine the value of the memory cell. Forexample, the value stored on the memory cell may be determined based onwhether the voltage at a node of the amplifier capacitor is higher thanthe reference voltage or lower than the reference voltage, with thedifference between these high and low voltages sometimes referred to asa sense window. A larger sense window may be desirable because it mayenable more accurate read operations.

In some cases, the amplifier capacitor may be coupled with a signal noderather than coupled directly with the digit line. The signal node may beselectively coupled with the digit line during the read operation, andthe value of the memory cell may be determined based on the voltage atthe signal node (which may, in turn, be based on the voltage across theamplifier capacitor). Such an approach may allow the voltage of thesignal node to be adjusted up or down independently of the digit line.For example, the voltage of the signal node may be shifted down at theend of a read operation to enable the use of a low-voltage latch.

In some cases, the voltage of the signal node may be “boosted” (e.g.,increased) at the beginning of the read operation, prior to coupling thedigit line with the signal node. Such a boost may increase theefficiency or accuracy of the read operation. The voltage boost may beimplemented by coupling the amplifier capacitor between the signal nodeand a voltage source and increasing the voltage of the voltage source.In some cases, it may be beneficial to use a large amplifier capacitor(in terms of capacitance) for this boost operation to reduce the impactof the parasitic capacitance associated with the memory circuit andprovide a faster, more efficient boosting operation.

The size of the amplifier capacitor may affect the quality orperformance of the read operation in other ways. For example, althoughthe total amount of charge transferred between the memory cell and theamplifier capacitor depends on the initial value stored on the memorycell, there is some amount of charge that is initially transferred atthe beginning of a read operation that is the same regardless of thevalue stored on the memory cell. This charge may be referred to as the“displacement charge” or “common mode charge” and may be a chargeassociated with increasing a bias voltage across the memory cell (e.g.,across the ferroelectric capacitor in the cell). The displacement chargemay not be useful for the read operation because it may be the sameregardless of the value stored on the memory cell. In some cases, thedisplacement charge may be relatively large compared with what may bereferred to as the “polar charge” that represents the value stored onthe memory cell. The polar charge may be a charge that remains stored onthe memory cell after a write operation when the bias voltage across thecell decreases to essentially zero and may represent the value stored onthe cell. Because the displacement charge is larger than the polarcharge, once all the charge (the displacement charge and the polarcharge) is integrated on the amplifier capacitor during the readoperation, there may be a relatively small difference between a voltagerepresenting a “1” value and a voltage representing a “0” value (e.g., asmall sense window). This may lead to less reliable read operations.

A small amplifier capacitor may provide better fidelity for the polarcharge and therefore provide a larger sense window but may becomesaturated by the larger initial displacement charge. A larger amplifiercapacitor may provide an efficient boost operation and accommodate alarge displacement charge amount but may lead to a relatively smallsense window. In some examples, a sense amplifier as described hereinmay utilize split capacitors (e.g., multiple separate capacitors) ratherthan a single amplifier capacitor, which may provide certain benefits inview of this tradeoff.

Features of the disclosure introduced above are further described belowin the context of FIGS. 1 through 3. Specific examples and benefits arethen described with respect to FIGS. 4 through 10. These and otherfeatures of the disclosure are further illustrated by and described withreference to apparatus diagrams, system diagrams, and flowcharts thatrelate to techniques for reading a memory cell using a sense amplifierwith split capacitors. Although the discussion herein primarily focuseson ferroelectric memory cells, similar techniques may be used for othertypes of memory cells, such as DRAM or other types of memory cells,without departing from the scope of the disclosure.

FIG. 1 illustrates an example of a memory array 100 that supportstechniques for reading a memory cell using a sense amplifier with splitcapacitors in accordance with aspects of the present disclosure. FIG. 1is an illustrative schematic representation of various components andfeatures of the memory array 100. As such, it should be appreciated thatthe components and features of the memory array 100 are shown toillustrate functional interrelationships, not their actual physicalpositions within the memory array 100. Memory array 100 may also bereferred to as an electronic memory apparatus or device. Memory array100 includes memory cells 105 that are programmable to store differentstates. In some cases, each memory cell 105 may be a ferroelectricmemory cell that may include a capacitor with a ferroelectric materialas the insulating material. In some cases, each memory cell 105 may beprogrammable to store one of two states, denoted as a logic 0 and alogic 1. Each memory cell 105 may be stacked on top of each otherresulting in two decks of memory cells 145. Hence, the example in FIG. 1may be an example that depicts two decks of memory array.

In some cases, memory cells 105 are configured to store one of more thantwo logic states. A memory cell 105 may store a charge representative ofthe programmable states in a capacitor; for example, a charged anduncharged capacitor may represent two logic states, respectively. DRAMarchitectures may commonly use such a design, and the capacitor employedmay include a dielectric material with paraelectric or linearpolarization properties as the insulator. By contrast, a ferroelectricmemory cell may include a capacitor with a ferroelectric material as theinsulating material. Different levels of charge of a ferroelectriccapacitor may represent different logic states. Ferroelectric materialshave non-linear polarization properties; some details and advantages ofa ferroelectric memory cell 105 are discussed below.

Operations such as reading and writing, which may be referred to asaccess operations, may be performed on memory cells 105 by activating orselecting word line 110 and digit line 115. Word lines 110 may also beknown as row lines, sense lines, and access lines. Digit lines 115 mayalso be known as bit lines, column lines, and access lines. Referencesto word lines and digit lines, or their analogues, are interchangeablewithout loss of understanding or operation. Word lines 110 and digitlines 115 may be perpendicular (or nearly perpendicular) to one anotherto create an array. Depending on the type of memory cell (e.g., FeRAM,RRAM), other access lines may be present (not shown), such as platelines, for example. It should be appreciated that the exact operation ofthe memory device may be altered based on the type of memory cell and/orthe specific access lines used in the memory device.

Asserting (e.g., activating or selecting) a word line 110 or a digitline 115 may include applying a voltage to the respective line. Wordlines 110 and digit lines 115 may be made of conductive materials suchas metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W)),metal alloys, carbon, conductively-doped semiconductors, or otherconductive materials, alloys, compounds, or the like.

Memory array 100 may be a two-dimensional (2D) memory array or athree-dimensional (3D) memory array. A 3D memory array may include 2Dmemory arrays formed on top of one another. This may increase the numberof memory cells that may be placed or created on a single die orsubstrate as compared with 2D arrays, which in turn may reduceproduction costs or increase the performance of the memory array, orboth. Memory array 100 may include any number of levels. Each level maybe aligned or positioned so that memory cells 105 may be approximatelyaligned with one another across each level. Each row of memory cells 105may be connected to a single word line 110, and each column of memorycells 105 may be connected to a single digit line 115. By activating oneword line 110 and one digit line 115 (e.g., applying a voltage to theword line 110 or digit line 115), a single memory cell 105 may beaccessed at their intersection. Accessing the memory cell 105 mayinclude reading or writing the memory cell 105. The intersection of aword line 110 and digit line 115 may be referred to as an address of amemory cell.

In some architectures, the logic storing device of a cell, e.g., acapacitor, may be electrically isolated from the digit line by aselector device. The word line 110 may be connected to and may controlthe selector device. For example, the selector device may be atransistor (e.g., thin-film transistor (TFT)) and the word line 110 maybe connected to the gate of the transistor. Activating the word line 110results in an electrical connection or closed circuit between thecapacitor of a memory cell 105 and its corresponding digit line 115. Thedigit line may then be accessed to either read or write the memory cell105. In addition, as described below in FIG. 2, access operation offerroelectric memory cells may need an additional connection to a nodeof the ferroelectric memory cell, namely a cell plate node via a plateline.

Accessing memory cells 105 may be controlled through a row decoder 120and a column decoder 130. For example, a row decoder 120 may receive arow address from the memory controller 140 and activate the appropriateword line 110 based on the received row address. Similarly, a columndecoder 130 receives a column address from the memory controller 140 andactivates the appropriate digit line 115. For example, memory array 100may include multiple word lines 110, labeled WL_1 through WL_M, andmultiple digit lines 115, labeled DL_1 through DL_N, where M and Ndepend on the array size. Thus, by activating a word line 110 and adigit line 115, e.g., WL_2 and DL_3, the memory cell 105 at theirintersection may be accessed. In addition, an access operation offerroelectric memory cells may need to activate a corresponding plateline for the memory cell 105, associated with plate line decoder (notshown).

Upon accessing, a memory cell 105 may be read, or sensed, by sensecomponent 125 to determine the stored state of the memory cell 105. Forexample, after accessing the memory cell 105, the ferroelectriccapacitor of memory cell 105 may discharge onto its corresponding digitline 115. Discharging the ferroelectric capacitor may result frombiasing, or applying a voltage, to the ferroelectric capacitor. Thedischarging may cause a change in the voltage of the digit line 115,which sense component 125 may compare to a reference voltage (not shown)in order to determine the stored state of the memory cell 105. Forexample, if digit line 115 has a higher voltage than the referencevoltage, then sense component 125 may determine that the stored state inmemory cell 105 was a logic 1 and vice versa. Sense component 125 mayinclude various transistors, capacitors, and amplifiers in order todetect and amplify a difference in the signals. The detected logic stateof memory cell 105 may then be output through column decoder 130 asoutput 135. In some cases, sense component 125 may be part of a columndecoder 130 or row decoder 120. Or, sense component 125 may be connectedto or in electronic communication with column decoder 130 or row decoder120. In some cases, sense component 125 may include a latch to latch thevalue of the memory cell (e.g., based on the detected logic state).

In some examples, the sense component 125 may include split capacitorsthat may be coupled with a selected digit line 115 to cause a transferof electric charge between the split capacitors and memory cell 105during a read operation of the memory cell. The amount of chargetransferred between memory cell 105 and one or both of the splitcapacitors may correspond to a logic state of the memory cell 105 (e.g.,a logic state of 1 or 0). Thus, one or both of the split capacitors maybe used to detect a signal from the memory cell 105 during the readoperation, since the voltage remaining on one or both of the splitcapacitors after some amount of electric charge has been transferredbetween the amplifier capacitor and memory cell 105 is indicative of thelogic state of memory cell 105.

A memory cell 105 may be set, or written, by similarly activating therelevant word line 110 and digit line 115—e.g., a logic value may bestored in the memory cell 105. Column decoder 130 or row decoder 120 mayaccept data, for example input/output 135, to be written to the memorycells 105. A ferroelectric memory cell 105 may be written by applying avoltage across the ferroelectric capacitor. This process is discussed inmore detail below.

In some memory architectures, accessing the memory cell 105 may degradeor destroy the stored logic state and re-write or refresh operations maybe performed to return the original logic state to memory cell 105. InDRAM, for example, the capacitor may be partially or completelydischarged during a sense operation, corrupting the stored logic state.So, the logic state may be re-written after a sense operation.Additionally, activating a single word line 110 may result in thedischarge of all memory cells in the row; thus, several or all memorycells 105 in the row may need to be re-written.

In some memory architectures, including DRAM, memory cells may losetheir stored state over time unless they are periodically refreshed byan external power source. For example, a charged capacitor may becomedischarged over time through leakage currents, resulting in the loss ofthe stored information. The refresh rate of these so-called volatilememory devices may be relatively high, e.g., tens of refresh operationsper second for DRAM arrays, which may result in significant powerconsumption. With increasingly larger memory arrays, increased powerconsumption may inhibit the deployment or operation of memory arrays(e.g., power supplies, heat generation, material limits), especially formobile devices that rely on a finite power source, such as a battery. Asdiscussed below, ferroelectric memory cells 105 may have beneficialproperties that may result in improved performance relative to othermemory architectures.

The memory controller 140 may control the operation (e.g., read, write,re-write, refresh, discharge) of memory cells 105 through the variouscomponents, for example, row decoder 120, column decoder 130, and sensecomponent 125. In some cases, one or more of the row decoder 120, columndecoder 130, and sense component 125 may be co-located with the memorycontroller 140. Memory controller 140 may generate row and columnaddress signals in order to activate the desired word line 110 and digitline 115. Memory controller 140 may also generate and control variousvoltages or currents used during the operation of memory array 100.

In some examples, the memory controller 140 may control various phasesof a read operation. In some cases, the memory controller 140 maycontrol selection of a memory cell by activating a word line signal. Insome cases, the memory controller 140 may control various timingsassociated with coupling one or both of the split capacitors with asignal node and/or a voltage source by activating one or more controlsignals.

In general, the amplitude, shape, or duration of an applied voltage orcurrent discussed herein may be adjusted or varied and may be differentfor the various operations discussed in operating memory array 100.Further, one, multiple, or all memory cells 105 within memory array 100may be accessed simultaneously; for example, multiple or all cells ofmemory array 100 may be accessed simultaneously during an access (orwrite or program) operation in which all memory cells 105, or a group ofmemory cells 105, are set or reset to a single logic state. It should beappreciated that the exact operation of the memory device may be alteredbased on the type of memory cell and/or the specific access lines usedin the memory device. In some examples where other access lines e.g.,plate lines, may be present (not shown), a corresponding plate line thatis connected with a word line and a digit line may need to be activatedto access a certain memory cell 105 of the memory array. It should beappreciated that the exact operation of the memory device may vary basedon the type of memory cell and/or the specific access lines used in thememory device.

FIG. 2 illustrates an exemplary diagram 200 of a ferroelectric memorycell and circuit components that support techniques for reading a memorycell using a sense amplifier with split capacitors in accordance withaspects of the present disclosure. Circuit 200 includes a memory cell105-a, word line 110-a, digit line 115-a, and sense component 125-a,which may be examples of a memory cell 105, word line 110, digit line115, and sense component 125, respectively, as described with referenceto FIG. 1. Memory cell 105-a may include a logic storage component, suchas capacitor 205 that has a first plate, cell plate 230, and a secondplate, cell bottom 215. Cell plate 230 and cell bottom 215 may becapacitively coupled through a ferroelectric material positioned betweenthem. The orientation of cell plate 230 and cell bottom 215 may beflipped without changing the operation of memory cell 105-a. Circuit 200also includes selector device 220 and reference line 225. Cell plate 230may be accessed via plate line 210 and cell bottom 215 may be accessedvia digit line 115-a. As described above, various states may be storedby charging or discharging the capacitor 205.

The stored state of capacitor 205 may be read or sensed by operatingvarious elements represented in circuit 200. Capacitor 205 may be inelectronic communication with digit line 115-a. For example, capacitor205 can be isolated from digit line 115-a when selector device 220 isdeactivated, and capacitor 205 can be connected to digit line 115-a whenselector device 220 is activated. Activating selector device 220 may bereferred to as selecting memory cell 105-a. In some cases, selectordevice 220 is a transistor (e.g., thin-film transistor (TFT)) and itsoperation is controlled by applying a voltage to the transistor gate,where the voltage magnitude is greater than the threshold voltagemagnitude of the transistor. Word line 110-a may activate the selectordevice 220; for example, a voltage applied to word line 110-a is appliedto the transistor gate, connecting the capacitor 205 with digit line115-a.

In other examples, the positions of selector device 220 and capacitor205 may be switched, such that selector device 220 is connected betweenplate line 210 and cell plate 230 and such that capacitor 205 is betweendigit line 115-a and the other terminal of selector device 220. In suchexamples, selector device 220 may remain in electronic communicationwith digit line 115-a through capacitor 205. This configuration may beassociated with alternative timing and biasing for read and writeoperations.

Due to the ferroelectric material between the plates of ferroelectriccapacitor 205, and as discussed in more detail below, ferroelectriccapacitor 205 may not discharge upon connection to digit line 115-a. Inone scheme, to sense the logic state stored by ferroelectric capacitor205, word line 110-a may be biased to select memory cell 105-a and avoltage may be applied to plate line 210. In some cases, digit line115-a is virtually grounded and then isolated from the virtual ground,which may be referred to as “floating,” prior to biasing the plate line210 and word line 110-a.

Biasing the plate line 210 may result in a voltage difference (e.g.,plate line 210 voltage minus digit line 115-a voltage) acrossferroelectric capacitor 205. The voltage difference may yield a changein the stored charge on ferroelectric capacitor 205, where the magnitudeof the change in stored charge may depend on the initial state offerroelectric capacitor 205—e.g., whether the initial state stored alogic 1 or a logic 0. This may cause a change in the voltage of digitline 115-a based on the charge stored on ferroelectric capacitor 205.Operation of memory cell 105-a by varying the voltage to cell plate 230may be referred to as “moving the cell plate.”

The change in voltage of digit line 115-a may depend on its intrinsiccapacitance. That is, as charge flows through digit line 115-a, somefinite charge may be stored in digit line 115-a and the resultingvoltage may depend on the intrinsic capacitance. The intrinsiccapacitance may depend on physical characteristics, including thedimensions, of digit line 115-a. Digit line 115-a may connect manymemory cells 105 so digit line 115-a may have a length that results in anon-negligible capacitance (e.g., on the order of picofarads (pF)). Theresulting voltage of digit line 115-a may then be compared to areference (e.g., a voltage of reference line 225) by sense component125-a in order to determine the stored logic state in memory cell 105-a.Other sensing processes may be used.

In some examples, during a read operation, the voltage of digit line115-a may be set to an initial sensing voltage (e.g., before memory cell105 is coupled with digit line 115-a). When memory cell 105-a issubsequently coupled to digit line 115-a, the capacitor 205 of memorycell 105-a may begin to discharge onto digit line 115-a, therebybeginning signal development on digit line 115-a.

Sense component 125-a may include various transistors, capacitors, andamplifiers to detect and amplify a difference in signals. Sensecomponent 125-a may include a sense amplifier that receives and comparesthe voltage of digit line 115-a and reference line 225, which may be setto a reference voltage. The sense amplifier output may be driven to thehigher (e.g., a positive) or lower (e.g., negative or ground) supplyvoltage based on the comparison. For instance, if digit line 115-a has ahigher voltage than reference line 225, then the sense amplifier outputmay be driven to a positive supply voltage. Sense component 125-a mayinclude latch circuitry to latch the value of the memory cell.

In some cases, the sense amplifier may additionally drive digit line115-a to the supply voltage. Sense component 125-a may then latch theoutput of the sense amplifier and/or the voltage of digit line 115-a,which may be used to determine the stored state in memory cell 105-a,e.g., logic 1. Alternatively, if digit line 115-a has a lower voltagethan reference line 225, the sense amplifier output may be driven to anegative or ground voltage. Sense component 125-a may similarly latchthe sense amplifier output to determine the stored state in memory cell105-a, e.g., logic 0. The latched logic state of memory cell 105-a maythen be output, for example, through column decoder 130 as output 135with reference to FIG. 1.

In some examples, the sense amplifier may include split capacitors thatmay be used to for various purposes during a read operation, includingintegration of charge from the memory cell. For example, the senseamplifier may include an integrator capacitor and a separate boostcapacitor, along with associated switching components that may supportindependent coupling and decoupling of the integrator capacitor and/orthe separate boost capacitor between the signal node and a voltagesource. The split capacitors and associated switching components may beoperable to provide different capacitances during different portions ofa read operation. In another example, the sense amplifier may include anintegrator capacitor and a separate displacement capacitor that may becoupled in series between the digit line and the signal node and thatmay be operable to provide different capacitances during differentportions of a read operation.

In some cases, the sense amplifier may receive the voltage at a signalnode coupled with the integrator capacitor in the sense component 125-aand compare the voltage of the signal node with the reference voltage.The sense amplifier output may be driven to the higher (e.g., apositive) or lower (e.g., negative or ground) supply voltage based onthe comparison. In this case, the sense amplifier detects the value ofthe cell based on the voltage of the signal node rather than based onthe voltage of a digit line, for example.

To write a value to a memory cell 105-a, a voltage may be applied acrosscapacitor 205. Various methods may be used. In one example, selectordevice 220 may be activated through word line 110-a in order toelectrically connect capacitor 205 to digit line 115-a. A voltage may beapplied across capacitor 205 by controlling the voltage of cell plate230 (through plate line 210) and cell bottom 215 (through digit line115-a). To write a logic 0, cell plate 230 may be taken high, that is, apositive voltage may be applied to plate line 210, and cell bottom 215may be taken low, e.g., virtually grounding or applying a negativevoltage to digit line 115-a. The opposite process is performed to writea logic 1, where cell plate 230 is taken low and cell bottom 215 istaken high.

FIG. 3 illustrates an example of non-linear electrical properties withhysteresis curves 300-a and 300-b for a ferroelectric memory cell thatsupports techniques for reading a memory cell using a sense amplifierwith split capacitors in accordance with aspects of the presentdisclosure. Hysteresis curves 300-a and 300-b illustrate an exampleferroelectric memory cell writing and reading process, respectively.Hysteresis curves 300 depict the charge, Q, stored on a ferroelectriccapacitor (e.g., capacitor 205 of FIG. 2) as a function of a voltagedifference, V.

A ferroelectric material is characterized by a spontaneous electricpolarization, e.g., it maintains a non-zero electric polarization in theabsence of an electric field. Example ferroelectric materials includebarium titanate (BaTiO₃), lead titanate (PbTiO₃), lead zirconiumtitanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectriccapacitors described herein may include these or other ferroelectricmaterials. Electric polarization within a ferroelectric capacitorresults in a net charge at the ferroelectric material's surface andattracts opposite charge through the capacitor terminals. Thus, chargeis stored at the interface of the ferroelectric material and thecapacitor terminals. Because the electric polarization may be maintainedin the absence of an externally applied electric field for relativelylong times, even indefinitely, charge leakage may be significantlydecreased as compared with, for example, capacitors employed in DRAMarrays. This may reduce the need to perform refresh operations asdescribed above for some DRAM architectures.

Hysteresis curves 300-a and 300-b may be understood from the perspectiveof a single terminal of a capacitor. By way of example, if theferroelectric material has a negative polarization, positive chargeaccumulates at the terminal. Likewise, if the ferroelectric material hasa positive polarization, negative charge accumulates at the terminal.Additionally, it should be understood that the voltages in hysteresiscurves 300 represent a voltage difference across the capacitor and aredirectional. For example, a positive voltage may be realized by applyinga positive voltage to the terminal in question (e.g., a cell plate 230)and maintaining the second terminal (e.g., a cell bottom 215) at ground(or approximately zero volts (0V)).

A negative voltage may be applied by maintaining the terminal inquestion at ground and applying a positive voltage to the secondterminal—e.g., positive voltages may be applied to negatively polarizethe terminal in question. Similarly, two positive voltages, two negativevoltages, or any combination of positive and negative voltages may beapplied to the appropriate capacitor terminals to generate the voltagedifference shown in hysteresis curves 300-a and 300-b.

As depicted in hysteresis curve 300-a, the ferroelectric material maymaintain a positive or negative polarization with a zero voltagedifference, resulting in two possible charged states: charge state 305and charge state 310. According to the example of FIG. 3, charge state305 represents a logic 0 and charge state 310 represents a logic 1. Insome examples, the logic values of the respective charge states may bereversed to accommodate other schemes for operating a memory cell.

A logic 0 or 1 may be written to the memory cell by controlling theelectric polarization of the ferroelectric material, and thus the chargeon the capacitor terminals, by applying voltage. For example, applying anet positive voltage 315 across the capacitor results in chargeaccumulation until charge state 305-a is reached. Upon removing voltage315, charge state 305-a follows path 320 until it reaches charge state305 at zero voltage. Similarly, charge state 310 is written by applyinga net negative voltage 325, which results in charge state 310-a. Afterremoving negative voltage 325, charge state 310-a follows path 330 untilit reaches charge state 310 at zero voltage. Charge states 305-a and310-a may also be referred to as the remnant polarization (Pr) values,e.g., the polarization (or charge) that remains upon removing theexternal bias (e.g., voltage). The coercive voltage is the voltage atwhich the charge (or polarization) is zero.

To read, or sense, the stored state of the ferroelectric capacitor, avoltage may be applied across the capacitor. In response, the storedcharge, Q, changes, and the degree of the change depends on the initialcharge state—e.g., the final stored charge (Q) depends on whether chargestate 305-b or 310-b was initially stored. For example, hysteresis curve300-b illustrates two possible stored charge states 305-b and 310-b.Voltage 335 may be applied across the capacitor as discussed withreference to FIG. 2. In other cases, a fixed voltage may be applied tothe cell plate and, although depicted as a positive voltage, voltage 335may be negative. In response to voltage 335, charge state 305-b mayfollow path 340. Likewise, if charge state 310-b was initially stored,then it follows path 345. The final position of charge state 305-c andcharge state 310-c depend on a number of factors, including the specificsensing scheme and circuitry.

In some cases, the final charge may depend on the intrinsic capacitanceof the digit line connected to the memory cell. For example, if thecapacitor is electrically connected to the digit line and voltage 335 isapplied, the voltage of the digit line may rise due to its intrinsiccapacitance. So a voltage measured at a sense component may not be equalto voltage 335 and instead may depend on the voltage of the digit line.The position of final charge states 305-c and 310-c on hysteresis curve300-b may thus depend on the capacitance of the digit line and may bedetermined through a load-line analysis—e.g., charge states 305-c and310-c may be defined with respect to the digit line capacitance. As aresult, the voltage of the capacitor, voltage 350 or voltage 355, may bedifferent and may depend on the initial state of the capacitor.

By comparing the digit line voltage to a reference voltage, the initialstate of the capacitor may be determined. The digit line voltage may bethe difference between voltage 335 and the final voltage across thecapacitor, voltage 350 or voltage 355—e.g., (voltage 335-voltage 350) or(voltage 335-voltage 355). The reference voltage may be generated suchthat its magnitude is between the two possible voltages of the twopossible digit line voltages in order to determine the stored logicstate—e.g., if the digit line voltage is higher or lower than thereference voltage. For example, the reference voltage may be an averageof the two quantities, (voltage 335-voltage 350) and (voltage335-voltage 355). Upon comparison by the sense component, the senseddigit line voltage may be determined to be higher or lower than thereference voltage, and the stored logic value of the ferroelectricmemory cell (e.g., a logic 0 or 1) may be determined.

In some cases, the displacement charge may be the charge that appearswhen the voltage applied across the memory cell increases. Thedisplacement charge may represent the charge required to store or read avalue of “1” on a memory cell. In some cases, the charge required tostore or read a value of “1” may be less than the charge required tostore or read a value of “0.” For instance, with reference to theexample of FIG. 3, the displacement charge for a ferroelectric memorycell may be represented as:

Q(disp)=|(Q(305-a)−Q(305)|

In some cases, the polar charge may be the charge that remains stored onthe cell when the voltage across the cell is removed or decreases toessentially zero. The polar charge may represent the difference incharge required between storing or reading a value of “1” and storing avalue of “0,” and thus may represent the value stored on the memorycell. For instance, with reference to the example of FIG. 3, the polarcharge for a ferroelectric memory cell may be represented as:

Q(polar)=|(Q(305)+Q(310)|

In some examples, as described in more detail with respect to FIGS.4-13, a sense amplifier may include split capacitors (e.g., two separatecapacitors that may be coupled with each other in parallel or in series)that may be used during a read operation to determine the stored logicvalue of the memory cell. In some examples, the split capacitors mayprovide a higher capacitance during certain portions of the readoperation and a lower capacitance during other portions of the readoperation.

As discussed above, reading a memory cell that does not use aferroelectric capacitor may degrade or destroy the stored logic state. Aferroelectric memory cell, however, may maintain the initial logic stateafter a read operation. For example, if charge state 305-b is stored,the charge state may follow path 340 to charge state 305-c during a readoperation and, after removing voltage 335, the charge state may returnto initial charge state 305-b by following path 340 in the oppositedirection.

FIG. 4 illustrates an example of a circuit 400 that supports techniquesfor reading a memory cell using a sense amplifier with split capacitorsin accordance with aspects of the present disclosure. The circuit 400illustrates a simplified circuit configuration that highlights severalcircuit components that work together during a read operation, as willbe described in more detail with respect to FIGS. 5-7.

The circuit 400 includes a memory cell 404 and a digit line (DL) 410.The digit line 410 may be an example of the digit lines 115 describedwith reference to FIGS. 1 and 2. The memory cell 404 may be an exampleof the memory cells 105 described with reference to FIGS. 1 and 2. Asdescribed with reference to FIG. 1, digit line 410 may have or beassociated with an intrinsic capacitance, represented in circuit 400 bycapacitor 414.

The memory cell 404 may include a switching component 408 and acapacitor 406. In some cases, the capacitor 406 may be a ferroelectriccapacitor, such as capacitor 205 described with reference to FIG. 2. Thecapacitor 406 may store a logic state (e.g., a logic state of 1 or 0).The switching component 408 may be an example of the selector device 220described with reference to FIG. 2. In some cases, a plate of capacitor406 is coupled with a plate line 412.

The memory cell 404 may be associated with a word line 402. The wordline 402 may be an example of the word line 110 described with referenceto FIGS. 1 and 2. During an access operation (e.g., a read operation ora write operation), the word line signal WL may be activated (e.g.,asserted) on word line 402 to cause switching component 408 to couplethe capacitor 406 with the digit line 410, thereby coupling memory cell404 with digit line 410.

The digit line 410 may be selectively coupled with a signal node 428(SIG) via switching component 416. Signal node 428 may, in turn, beselectively coupled with latch 446 via switching components 440, 444.Latch 446 may determine and latch a value stored on memory cell 404based on a voltage of signal node 428. In some cases, latch 446 maydetermine the value based on a comparison of a voltage of signal node428 with a reference voltage, as described with reference to FIG. 1.

Circuit 400 includes variable (e.g., configurable) capacitive component430, which includes two split capacitors, boost capacitor 434 (BOOSTCAP)and integrator capacitor 438 (INTCAP), along with switching components432, 436. Variable capacitive component 430 may be an alternative to ora substitute for a conventional amplifier capacitor, for example.

Boost capacitor 434 and/or integrator capacitor 438 may be capacitorshaving different capacitances or the same capacitances. In some cases,boost capacitor 434 may have a larger capacitance than integratorcapacitor 438. Boost capacitor 434 may be so-named because it may beused for a boost operation during a read operation of the memory cell,as described herein. Integrator capacitor 438 may be so-named because itmay be used along with an amplifier (e.g., a differential amplifier, notshown) to integrate charge transferred between memory cell 404 andintegrator capacitor 438 during a read operation of memory cell 404.

In some cases, switching components 432, 436 may be independentlyactivated or deactivated (e.g., selected or deselected) by activating ordeactivating independent control signals CS1, CS2, respectively. In somecases, switching components 432, 436 may each be or include a transistor(e.g., a metal-oxide-semiconductor (MOS) transistor). A control signalCS1, CS2 may be provided to the gate of the respective transistor toactivate the switching component 432, 436.

In the example of circuit 400, boost capacitor 434 is coupled withsignal node 428 and is configured to be selectively coupled with avoltage source 426 via switching component 432. Integrator capacitor 438is coupled with signal node 428 and is configured to be selectivelycoupled with voltage source 426 via switching component 436. Thus, boostcapacitor 434 may be selectively coupled in parallel with integratorcapacitor 438 such that a first node of boost capacitor 434 is coupledwith a first node of integrator capacitor 438, and a second node ofboost capacitor 434 is coupled with a second node of integratorcapacitor 438. In some cases, the voltage of signal node 428 may besubstantially equivalent to a voltage at a node of integrator capacitor438 and/or boost capacitor 434.

In the example of circuit 400, boost capacitor 434 is configured to becoupled between signal node 428 and voltage source 426 independently ofintegrator capacitor 438, via switching component 432 and control signalCS1. Similarly, integrator capacitor 438 is configured to be coupledbetween signal node 428 and voltage source 426 independently of boostcapacitor 434, via switching component 436 and control signal CS2.

The total capacitance of variable capacitive component 430 may depend onthe state of switching components 432, 436; e.g., on whether each isactivated (closed) or deactivated (open). For example, when bothswitching components 432, 436 are activated such that boost capacitor434 is coupled between signal node 428 and voltage source 426 inparallel with integrator capacitor 438, the combined capacitance betweensignal node 428 and voltage source 426 due to variable capacitivecomponent 430 may be expressed as the sum of the capacitances of boostcapacitor 434 and integrator capacitor 438. When boost capacitor 434 isdecoupled from voltage source 426 (e.g., switching component 432 isdeactivated) and integrator capacitor 438 is coupled between signal node428 and voltage source 426, the capacitance between signal node 428 andvoltage source 426 due to variable capacitive component 430 may be thecapacitance of integrator capacitor 438 and may not include thecapacitance of boost capacitor 434.

Voltage source 426 may be referred to as a “boost and shift” voltagesource (VBNS) since it may be used to adjust the voltage of signal node428 during portions of a read operation by boosting (e.g., increasing)the voltage of signal node 428 and/or shifting (e.g., decreasing) thevoltage of signal node 428.

In some cases, voltage source 426 may be used to increase the voltage ofsignal node 428 via variable capacitive component 430 (e.g., via boostcapacitor 434 and/or integrator capacitor 438) during a first portion ofa read operation.

Optionally, voltage source 426 may be used to shift the voltage ofsignal node 428 via variable capacitive component 430 (e.g., via boostcapacitor 434 and/or integrator capacitor 438) during or after a secondportion of a read operation. For example, voltage source 426 may be usedto shift the voltage of signal node 428 down prior to latching the valuestored on the memory cell 404 to enable the use of a low-voltage latch.

Circuit 400 includes additional voltage sources 420, 424, 442. Voltagesource 420 (VPCH) may be used to pre-charge digit line 410 at thebeginning of a read operation. Voltage source 424 (VREF) may be used togenerate a reference voltage that may be used to determine a valuestored on memory cell 404 during a read operation. Voltage source 442(VSF) may be used to provide a voltage for switching component 440 whenswitching component 440 operates as a source follower (SF) during theread operation.

In some cases, switching components 408, 416, 418, 422, 432, 436, 440,and/or 444 may be or may include one or more transistors that may beused to couple various elements of circuit 400 by activating (e.g.,asserting) a signal (e.g., WL, CS1, CS2) at a gate of the transistor(s).In some cases, switching component 416 may include two or moretransistors in a cascode configuration. Switching component 440 may be atransistor that is configured to operate as a source follower (SF).

In some cases, it may be desirable for variable capacitive component 430to provide a relatively large capacitance during the boost portion ofthe read operation (e.g., during the portion when voltage source 426boosts the voltage of signal node 428). A large capacitance may bedesirable to offset the effect of the intrinsic capacitance of digitline 410, as represented by capacitor 414, and provide a more efficient(e.g., faster) boost operation.

In some cases, a large capacitance may also be desirable during adisplacement charge portion of the read operation, during which some orall of the displacement charge is transferred between the memory celland the variable capacitive component after memory cell 404 is coupledwith digit line 410 during the read operation. A large capacitance maybe desirable to absorb (or provide) the displacement charge from (or to)memory cell 404 and ensure that the capacitor used for integrating thecharge during signal development (e.g., during a portion of the readoperation when the memory cell is coupled with the digit line) does notbecome saturated.

Thus, in some cases, variable capacitive component 430 may be configuredwith boost capacitor 434 coupled in parallel with integrator capacitor438 during a first portion of the read operation, which may include theboost portion and/or the displacement charge portion.

In some cases, it may be desirable for variable capacitive component 430to provide a relatively low (e.g., small, in terms of capacitance ormicrofarads) capacitance during a second portion of the read operation,when the polar charge is transferred between the memory cell and thevariable capacitive component 430, after some or all of the displacementcharge has been transferred. The polar charge may be an amount of chargethat is less than the displacement charge, for example. During thesecond portion of the read operation, a smaller capacitance than duringthe first portion of the read operation may provide better accuracy forthe read operation by providing a more faithful representation of thepolar charge and thereby increasing the sense window, for example.

Thus, in some cases, variable capacitive component 430 may be configuredwith boost capacitor 434 decoupled from integrator capacitor 438 (e.g.,decoupled from voltage source 426 by deactivating switching component432) during the second portion of the read operation, such that thecapacitance of variable capacitive component 430 is equal to thecapacitance of integrator capacitor 438.

In some cases, the value of the memory cell 404 may be determined basedon a voltage across integrator capacitor 438 after the signaldevelopment portion of the operation or based on a voltage of the signalnode 428 (which may be substantially equivalent to the voltage of a nodeof the integrator capacitor 438 since the nodes are coupled).

The operation and interaction of the components depicted in circuit 400is described in more detail with reference to the timing diagrams ofFIGS. 5-7.

FIG. 5 illustrates an example of a timing diagram 500 that supportsreading a memory cell using a sense amplifier with split capacitors inaccordance with aspects of the present disclosure. The timing diagram500 shows various voltage levels associated with the components of thecircuit 400 described with reference to FIG. 4 to illustrate how thetechniques for reading a memory cell using a sense amplifier with splitcapacitors to provide a fast and reliable read operation.

Timing diagram 500 may correspond to operation of circuit 400 using whatmay be referred to as a “single boost” approach. The read operation maycorrespond to a time period between t0 and t3 that may include a boostportion and a signal development portion.

At time t0, control signals CS1, CS2 are activated (e.g., by increasingthe voltage V_(CS1) 510 and V_(CS2) 505) to couple the boost capacitor(e.g., boost capacitor 434) and integrator capacitor (e.g., integratorcapacitor 438) in parallel between the signal node (e.g., signal node428) and a voltage source (e.g., voltage source 426). While controlsignals CS1 and CS2 are depicted as being activated substantiallysimultaneously in timing diagram 500, in some examples, they may beactivated at different times occurring before time t1.

At time t1, the voltage of the voltage source (not shown) is increasedto boost the voltage of the signal node V_(SIG) 515 via the boostcapacitor and the integrator capacitor; that is, increasing the voltageof the voltage source increases the voltages across the boost capacitorand the integrator capacitor, thereby increasing the voltage of thesignal node V_(SIG) 515, which is coupled with the boost capacitor andthe integrator capacitor. The boost portion 525 of the read operationmay occur between time t1 and time t2, while the boost capacitor and theintegrator capacitor are coupled in parallel between the signal node andthe voltage source. During the boost portion of the read operation, thecapacitance of the variable capacitive component (e.g., variablecapacitive component 430) is the sum of the capacitance of the boostcapacitor and the integrator capacitor. Thus, during the boost portionof the read operation, the capacitance of the variable capacitivecomponent is relatively large (e.g., as compared to the capacitance ofthe variable capacitive component during the subsequent signaldevelopment portion 530 of the read operation).

At time t2, the word line signal WL is asserted (e.g., by increasing thevoltage of the word line, V_(WL) 520) to couple the memory cell (e.g.,memory cell 404) with the digit line (e.g., digit line 410). In somecases, at time t2, the digit line may already be coupled with the signalnode via switching component 416; that is, switching component 416 mayalready be activated at time t2. The signal development portion 530 ofthe read operation may begin at time t2 when the word line signal isasserted.

Also at time t2 (or in some cases, shortly after time t2), controlsignal CS1 is deactivated to decouple the boost capacitor from thevoltage source, and thereby decouple the boost capacitor from beingcoupled in parallel with the integrator capacitor. When the boostcapacitor is decoupled, the capacitance of the variable capacitivecomponent changes from being the sum of the capacitance of the boostcapacitor and the integrator capacitor to being only the capacitance ofthe integrator capacitor.

In some examples, coupling the memory cell with the digit line casescharge to be transferred between the memory cell and the variablecapacitive component (e.g., between the memory cell and the boostcapacitor and/or the integrator capacitor, depending on the status ofcontrol signals CS1 and CS2) via the digit line and signal node. In theexample of FIG. 5, coupling the memory cell with the digit line causescharge transfer between the memory cell and the integrator capacitorsince CS1 is deactivated, and thus, the boost capacitor is decoupledfrom the integrator capacitor during the signal development portion ofthe read operation. The charge transfer causes a change (e.g., adecrease) in the signal node voltage V_(SIG) 515. The charge transferredduring the signal development portion of the read operation may includethe displacement charge and some or all of the polar charge.

Thus, during the signal development portion 530 of the read operation,the capacitance of the variable capacitive component is equal to thecapacitance of the integrator capacitor, and is smaller than thecapacitance of the variable capacitive component during the boostportion 525 of the read operation.

The change in the signal node voltage V_(SIG) may depend on the valuestored on the memory cell at the beginning of the read operation; thus,FIG. 5 depicts two voltages that may be associated with reading a memorycell having a value of “1” or a value of “0.” The difference in the twopossible voltages of the signal node V_(SIG) 515 (or in some cases, ofthe voltage across the integrator capacitor) after the signaldevelopment portion of the read operation (e.g., at time t3) may bereferred to as the sense window; a larger sense window (e.g., a greaterdifference between the voltage associated with a “0” and the voltageassociated with a “1”) may be desirable, as it may enable a moreaccurate read operation. After the boost capacitor is decoupled at timet2, the capacitance of the variable capacitive component is relativelysmall, which may provide a larger sense window relative to the use ofthe larger capacitance used during the boost portion of the readoperation.

At time t3, the sense component may determine and latch the value storedon the memory cell based on the voltage of the signal node V_(SIG) 515.In some cases, the sense component may determine the value by comparingV_(SIG) 515 with a reference voltage (not shown).

In some cases, the voltage of the signal node is substantiallyequivalent to the voltage of a node of the integrator capacitor becausethe integrator capacitor is coupled with the signal node. Thus, thesense component may determine the value based on the voltage of thesignal node V_(SIG) 515 and/or based on a voltage across the integratorcapacitor.

FIG. 6 illustrates an example of a timing diagram 600 that supportsreading a memory cell using a sense amplifier with split capacitors inaccordance with aspects of the present disclosure. The timing diagram600 shows various voltage levels associated with the components of thecircuit 400 described with reference to FIG. 4 to illustrate how thetechniques for reading a memory cell using a sense amplifier with splitcapacitors to provide a fast and reliable read operation.

Timing diagram 600 may correspond to operation of circuit 400 using whatmay be referred to as a “double boost” approach. The read operation maycorrespond to a time period between t0 and t5 that includes a firstboost portion, a displacement charge portion, a second boost portion,and a polar charge portion.

At time t0, control signal CS1 is activated (e.g., by increasing thevoltage V_(CS1) 610) to couple the boost capacitor between the signalnode (e.g., signal node 428) and a voltage source (e.g., voltage source426). At time t0, the integrator capacitor is not coupled with thesignal node since control signal CS2 is deactivated (e.g., the voltageV_(CS2) 605 is low).

At time t1, the voltage of the voltage source (not shown) is increasedto boost the voltage of the signal node V_(SIG) 615 via the boostcapacitor; that is, increasing the voltage of the voltage sourceincreases the voltage across the boost capacitor, thereby increasing thevoltage of the signal node, which is coupled with the boost capacitor.The first boost portion 625 of the read operation may occur between timet1 and time t2, while the boost capacitor is coupled between the signalnode and the voltage source, and the integrator capacitor is uncoupledfrom the boost capacitor (e.g., control signal CS2 is deactivated).During the first boost portion of the read operation, the capacitance ofthe variable capacitive component (e.g., variable capacitive component430) is substantially equal to the capacitance of the boost capacitor.

At time t2, the word line signal WL is asserted (e.g., by increasing thevoltage of the word line, V_(WL) 620) to couple the memory cell (e.g.,memory cell 404) with the digit line (e.g., digit line 410). In somecases, at time t2, the digit line may already be coupled with the signalnode via switching component 416; that is, switching component 416 mayalready be activated at time t2. The displacement charge portion 630 ofthe read operation may begin at time t2 when the word line signal isasserted to couple the memory cell with the digit line. In some cases,coupling the memory cell with the digit line causes charge transferbetween the memory cell and the boost capacitor (e.g., via the signalnode). From time t2 to t3, some or all of the displacement charge may betransferred between the memory cell and the boost capacitor.

At time t3, control signal CS1 is deactivated (e.g., by lowering thevoltage V_(CS1) 610) to decouple the boost capacitor from the voltagesource. When the boost capacitor is decoupled, the capacitance of thevariable capacitive component changes from being substantiallyequivalent to the capacitance of the boost capacitor to beingsubstantially zero (since neither the boost capacitor nor the integratorcapacitor are coupled between the signal node and the voltage sourcebetween t3 and t4). Thus, the voltage of the signal node V_(SIG) 615begins to rise due to charge sharing between the memory cell and thesignal node. The period between time t3 and t4 may be referred to as thesecond boost portion 635 of the read operation.

In some cases, the time t3 at which the boost capacitor is decoupledfrom the voltage source is based on a fixed time delay relative to thetime at which the word line signal is activated; e.g., relative to thetime at which the memory cell is coupled with the digit line.

In some cases, the time t3 at which the boost capacitor is decoupledfrom the voltage source is based on a comparison of a voltage at a nodeof the boost capacitor with a voltage of the digit line. For example,the boost capacitor may be decoupled at a time when the voltage at anode of the boost capacitor is equal to the voltage of the digit line.

At time t4, control signal CS2 is activated to couple the integratorcapacitor with the voltage source (e.g., by increasing the voltageV_(CS2) 605 to activate switching component 436), and thereby couple theintegrator capacitor between the signal node and the voltage source.Thus, at time t4, the capacitance of the variable capacitive componentis substantially equivalent to the capacitance of the integratorcapacitor. In some cases, coupling the integrator capacitor between thesignal node and the voltage source causes charge transfer between thememory cell and the integrator capacitor. Beginning at time t4, some orall of the polar charge may be transferred between the memory cell andthe integrator capacitor. The time period from t4-t5 may be referred toas the polar charge portion 640 of the read operation.

In some cases, the time t4 at which the integrator capacitor is coupledwith the signal node is based on a fixed time delay after the time atwhich the boost capacitor is decoupled from the signal node; e.g., timet3.

At time t5, the sense component may determine and latch the value storedon the memory cell based on the voltage of the signal node V_(SIG) 615as described with respect to FIG. 5.

As previously discussed, the voltage of the signal node may besubstantially equivalent to the voltage of a node of the integratorcapacitor. Thus, the sense component may determine the value based onthe voltage of the signal node V_(SIG) 615 and/or based on a voltageacross the integrator capacitor.

FIG. 7 illustrates an example of a timing diagram 700 that supportsreading a memory cell using a sense amplifier with split capacitors inaccordance with aspects of the present disclosure. The timing diagram700 illustrates various signals during a read operation using a senseamplifier with a variable capacitive component. The read operation maycorrespond to a time period between t0 and t4 that includes a firstportion of the read operation and a second portion of the readoperation. The timing diagram 700 shows various voltage levelsassociated with the components of the circuit 400 described withreference to FIG. 4 to illustrate how the techniques for reading amemory cell using a sense amplifier with a variable capacitive componentto provide a fast and reliable read operation.

Timing diagram 700 may correspond to operation of circuit 400 using whatmay be referred to as a “non-linear capacitor” approach, because it maycause the variable capacitance component to provide a non-linearcapacitance characteristic during a read operation. Compared to timingdiagram 500, timing diagram 700 illustrates that control signal CS1,which couples the boost capacitor in parallel with the integratorcapacitor between the signal node and the voltage source, remains activefor a longer period of time after the word line signal V_(WL) isasserted.

In this approach, the boost capacitor may be coupled in parallel withthe integrator capacitor to provide a larger capacitance duringdisplacement charge transfer and decoupled to provide a smallercapacitance during the polar charge transfer. Thus, a larger capacitancemay be used for the boost portion and to absorb (or provide) some or allof the displacement charge, after which a smaller capacitance may beused to integrate the polar charge.

At time t0, control signals CS1, CS2 are activated (e.g., by increasingthe voltage V_(CS1) 705 and V_(CS2) 710) to couple the boost capacitorand integrator capacitor in parallel between the signal node and avoltage source.

At time t1, the voltage source is increased to boost the voltage of thesignal node V_(SIG) 715 via the boost capacitor and the integratorcapacitor. During this portion of the read operation, the capacitance ofthe variable capacitive component is relatively large, since the boostcapacitor and the integrator capacitor are coupled in parallel. The timeperiod between t1 and t2 may be referred to as the boost portion 725 ofthe read operation.

At time t2, the word line signal WL is asserted (e.g., by increasing thevoltage of the word line, V_(WL) 720) to couple the memory cell with thedigit line. In some cases, at time t2, the digit line may already becoupled with the signal node via switching components. The time betweent2 and t3 may be referred to as the displacement charge portion 730 ofthe read operation. In some examples, coupling the memory cell with thedigit line may cause charge transfer between the memory cell and thevariable capacitive component (e.g., between the memory cell and theboost capacitor and/or the integrator capacitor, depending on the statusof control signals CS1 and CS2). During the displacement charge portion730 of the read operation, some or all of the displacement charge istransferred between the memory cell and the variable capacitivecomponent via the signal node. The charge transfer causes a change(e.g., a decrease) in the signal node voltage V_(SIG) 715.

At time t3, control signal CS1 is deactivated (e.g., by lowering thevoltage of V_(CS1) 710) to decouple the boost capacitor from the voltagesource, thereby decoupling the boost capacitor from being coupled inparallel with the integrator capacitor. Thus, at time t3, thecapacitance of the variable capacitive component may be substantiallyequivalent to the capacitance of the integrator capacitor.

After time t3, charge continues to be transferred between the memorycell and the integrator capacitor. This charge may include the polarcharge, and, in some cases, may include a portion of the displacementcharge if the displacement charge was not fully transferred between thememory cell and the variable capacitive component before time t3. Thetime period between t3 and t4 may be referred to as the polar chargeportion 735 of the read operation.

At time t4, after some or all of the polar charge has been transferredbetween the memory cell and the integrator capacitor, the sensecomponent may determine and latch the value stored on the memory cellbased on the voltage of the signal node V_(SIG) 715 and/or the voltageacross the integrator capacitor.

In some cases, the time at which the boost capacitor is decoupled, timet3, is based on a fixed delay (e.g., a fixed amount of elapsed time)relative to the time at which the word line signal V_(WL) 720 isasserted; e.g., a fixed delay after coupling the memory cell with thedigit line. In some cases, time t3 is based on an amount of chargeaccumulated on the boost capacitor; e.g., a time at which a certainamount of displacement charge has been accumulated on the boostcapacitor. In some cases, time t3 is based on a time at which the boostcapacitor is fully discharged; e.g., a time at which the boost capacitormay no longer transfer charge to the memory cell.

In some cases, the non-linear capacitor approach described with respectto timing diagram 700 may provide a better (e.g., larger) sense windowrelative to some other approaches since the voltage associated with a“1” value remains higher due to the relatively high capacitance of thevariable capacitance component between t2 and t3 (during thedisplacement charge portion, in which the boost capacitor and integratorcapacitor are coupled in parallel).

FIGS. 8A-8D depict exemplary variable capacitive components 830-a,830-b, 830-c, 830-d that support reading a memory cell using a senseamplifier with split capacitors in accordance with aspects of thepresent disclosure. Variable capacitive components 830-a, 830-b, 830-c,830-d may be examples of or alternatives to variable capacitivecomponent 430 as depicted in FIG. 4.

FIG. 8A depicts variable capacitive component 830-a, which includes aboost capacitor 834, integrator capacitor 838, and switching components832, 836 that may be controlled using control signals CS1 and CS2,respectively. In exemplary variable capacitive component 830-a, boostcapacitor 834 and integrator capacitor 838 are configured to beindependently coupled and decoupled with voltage source 826 viaswitching components 832 and 836. Because boost capacitor and integratorcapacitor are both coupled with signal node 828, coupling boostcapacitor 834 and integrator capacitor 838 with voltage source 826couples boost capacitor 834 and integrator capacitor 838 in parallelbetween signal node 828 and voltage source 826. In some cases, switchingcomponents 832, 836 may be n-type transistors.

FIG. 8B depicts variable capacitive component 830-b, which may provideanother alternative to variable capacitive component 430. In exemplaryvariable capacitive component 830-b, boost capacitor 834 and integratorcapacitor 838 are configured to be independently coupled and decoupledwith signal node 828 via switching components 848 and 850. Because boostcapacitor and integrator capacitor are coupled with voltage source 826,coupling boost capacitor 834 and integrator capacitor 838 with signalnode 828 (e.g., by activating CS1 and CS2) couples boost capacitor 834and integrator capacitor 838 in parallel between signal node 828 andvoltage source 826. In some cases, switching components 848, 850 may bep-type transistors.

FIG. 8C depicts variable capacitive component 830-c, which may provideanother alternative to variable capacitive component 430. Variablecapacitive component 830-c provides an example of a variable capacitivecomponent that requires a single switching component 832 and controlsignal (CS1). In variable capacitive component 830-c, integratorcapacitor 838 is directly coupled (e.g., hardwired) between signal node828 and voltage source 826 without a switching component. Thus, theoperation of variable capacitive component 830-c may be similar to thatdescribed with respect to variable capacitive component 430 with controlsignal CS2 always activated. Boost capacitor 834 is configured to beindependently coupled and decoupled with voltage source 826 viaswitching component 832. Because integrator capacitor is coupled withvoltage source 826 and signal node 828, coupling boost capacitor 834with voltage source 826 (e.g., by activating CS1) couples boostcapacitor 834 and integrator capacitor 838 in parallel between signalnode 828 and voltage source 826. In some cases, switching component 832may be an n-type transistor.

FIG. 8D depicts variable capacitive component 830-d, which may provideanother alternative to variable capacitive component 430. Like variablecapacitive component 830-c, variable capacitive component 830-d requiresa single switching component 848 and control signal (CS1). In variablecapacitive component 830-d, integrator capacitor 838 is coupled (e.g.,hardwired) between signal node 828 and voltage source 826. Thus, theoperation of variable capacitive component 830-c may be similar to thatdescribed with respect to variable capacitive component 430 with controlsignal CS2 always activated. Boost capacitor 834 is configured to beindependently coupled and decoupled with signal node 828 via switchingcomponent 848. Because integrator capacitor is coupled with voltagesource 826 and signal node 828, coupling boost capacitor 834 with signalnode 828 (e.g., by activating CS1) couples boost capacitor 834 andintegrator capacitor 838 in parallel between signal node 828 and voltagesource 826. In some cases, switching component 848 may be a p-typetransistor.

FIG. 9 illustrates an example of a variable capacitive component 902that supports reading a memory cell using a sense amplifier with splitcapacitors in accordance with certain aspects of the disclosure.Variable capacitive component 902 may be an alternative to variablecapacitive component 430, for example, and may include non-linearintegrator capacitor 904. Non-linear integrator capacitor 904 may be anMOS capacitor, the source and drain of which may be coupled togethersuch that the gate capacitance of the MOS capacitor comprises anon-linear capacitor, which may be desirable because when the voltageacross an MOS capacitor is lower than the threshold voltage, thecapacitance of the non-linear capacitor decreases, thereby potentiallyproviding a better sense window.

In some cases, non-linear integrator capacitor 904 may be substitutedfor integrator capacitor 838 in any one of the variable capacitivecomponents 830 described with respect to FIG. 8. In some cases, the useof a non-linear integrator capacitor 904 may result in similar waveformsas depicted in timing diagram 700. In some cases, the use of anon-linear integrator capacitor 904 may enable similar or betterperformance (in terms of increasing the sense window) relative to thatdescribed with respect to the non-linear timing of timing diagram 700.

FIG. 10 illustrates an example of a circuit 1000 that supportstechniques for reading a memory cell using a sense amplifier with splitcapacitors in accordance with aspects of the present disclosure. Circuit1000 illustrates a simplified circuit configuration that highlightsseveral circuit components that work together during a read operation.

As previously discussed, in some cases, it may be desirable to have arelatively high (e.g., large, in terms of capacitance or microfarads)capacitance of an amplifier capacitor while the displacement charge istransferred between the memory cell and the amplifier capacitor, but itmay be desirable to have a relatively small capacitance of an amplifiercapacitor when the polar charge is transferred between the memory celland the amplifier capacitor (e.g., after some or all of the displacementcharge has been transferred between the amplifier capacitor and thememory cell). Circuit 1000 provides an example of using split capacitorsto achieve both of these objectives. Circuit 1000 may be an alternativeto circuit 400 and may provide similar benefits without the use ofswitching components (e.g., switching components 432, 436) and controlsignals (e.g., CS1, CS2) associated with the split capacitors.

The circuit 1000 includes a memory cell 1004 and a digit line (DL) 1010.The digit line 1010 may be an example of the digit lines 115 describedwith reference to FIGS. 1 and 2. The memory cell 1004 may be an exampleof the memory cells 105 described with reference to FIGS. 1 and 2. Asdescribed with reference to FIG. 1, digit line 1010 may have or beassociated with an intrinsic capacitance, represented in circuit 1000 bycapacitor 1014 (CDL).

The memory cell 1004 may include a switching component 1008 and acapacitor 1006. In some cases, the capacitor 1006 may be an example of aferroelectric capacitor, such as capacitor 205 described with referenceto FIG. 2. The capacitor 1006 may store a logic state (e.g., a logicstate of 1 or 0). The switching component 1008 may be an example of theselector device 220 described with reference to FIG. 2.

The memory cell 1004 may be associated with a word line 1002. The wordline 1002 may be an example of the word line 110 described withreference to FIGS. 1 and 2. During an access operation (e.g., a readoperation or a write operation), the word line signal WL may beactivated (e.g., asserted) on word line 1002 to cause switchingcomponent 1008 to couple the capacitor 1006 with the digit line 1010.

The digit line 1010 may be selectively coupled with a signal node 1028(SIG) via switching component 1016. Signal node 1028 may, in turn, beselectively coupled with latch 1046 via switching components 1040, 1044.Latch 1046 may determine a value stored on memory cell 1004 based on avoltage of signal node 1028. In some cases, latch 1046 may determine thevalue based on a comparison of a voltage of signal node 1028 with areference voltage, as described with reference to FIG. 1.

Circuit 1000 includes displacement capacitor 1052 (DISPCAP) andintegrator capacitor 1038 (INTCAP). Displacement capacitor 1052 andintegrator capacitor 1038 are coupled in series between digit line 1010and signal node 1028. Displacement capacitor 1052 and integratorcapacitor 1038 are also coupled with voltage source 1026. Displacementcapacitor 1052 and integrator capacitor 1038 may be capacitors havingdifferent capacitances or the same capacitances. In some cases,displacement capacitor 1052 may have a larger capacitance thanintegrator capacitor 1038.

In some cases, the voltage of signal node 1028 may be equivalent to avoltage at a node of integrator capacitor 1038.

Voltage source 1026 may be used to adjust the voltage of signal node1028 during portions of a read operation by boosting (e.g., increasing)the voltage of signal node 1028 and/or shifting (e.g., decreasing) thevoltage of signal node 1028. In some cases, voltage source 1026 may beused to increase the voltage of signal node 1028 via integratorcapacitor 1038 during a first portion of a read operation; e.g., duringa boost portion of the read operation.

Optionally, voltage source 1026 may be used to shift the voltage ofsignal node 1028 via integrator capacitor 1038 during or after a secondportion of a read operation. For example, voltage source 1026 may beused to shift the voltage of signal node 1028 down prior to latching thevalue stored on the memory cell to enable the use of a low-voltagelatch.

Circuit 1000 includes additional voltage sources 1020, 1024, 1042.Voltage source 1020 (VPCH) may be used to pre-charge digit line 1010 atthe beginning of a read operation. Voltage source 1024 (VREF) may beused to generate a reference voltage that may be used to determine avalue stored on memory cell 1004 during a read operation. Voltage source1042 (VSF) may be used to provide a voltage for switching component 1040when switching component 1040 operates as a source follower.

In some cases, switching components 1008, 1016, 1018, 1022, 1040, and/or1044 may be or may include one or more transistors that may be used tocouple various elements of circuit 1000 by activating (e.g., asserting)a signal at a gate of the transistor(s). In some cases, switchingcomponent 1016 includes two or more transistors in a cascodeconfiguration. Switching component 1040 may be a transistor that isconfigured to operate as a source follower (SF) between voltage source1042 and latch 1046.

In the example of circuit 1000, displacement capacitor 1052 and digitline 1010 may be pre-charged to an initial voltage during a pre-chargingportion of the read operation. During a subsequent boost portion of theread operation (e.g., when the voltage of voltage source 1026 isincreased), the voltage of signal node 1028 is increased via integratorcapacitor 1038, and the voltage of the digit line 1010 is increased viadisplacement capacitor 1052. Increasing the voltage of the digit line1010 causes switching component 1016 to be deactivated since the voltageof the digit line 1010 is boosted higher than the threshold voltage ofswitching component 1016 and thus deactivates switching component 1016.

After the boost portion of the read operation (e.g., after switchingcomponent 1016 has been deactivated as described above), the word linesignal WL may be activated on word line 1002 to couple the memory cell1004 with the digit line 1010 and begin the signal development portionof the read operation. As previously discussed, the signal developmentportion includes a displacement charge portion during which thedisplacement charge is transferred between the memory cell and acapacitor(s), and a polar charge portion when the remaining polar chargeis transferred between the memory cell and the capacitor(s).

In circuit 1000, once switching component 1016 is deactivated and memorycell 1004 is coupled with digit line 1010, memory cell 1004 may begintransferring the displacement charge between memory cell 1004 anddisplacement capacitor 1052 via digit line 1010. Thus, displacementcapacitor 1052 may absorb or provide some or all of the displacementcharge transferred between displacement capacitor 1052 and memory cell1004. As the displacement charge is transferred between memory cell 1004and displacement capacitor 1052, the voltage of the digit line 1010 maychange, since the digit line 1010 is coupled with a node of thedisplacement capacitor 1052. In this manner, the voltage of the digitline 1010 may eventually return (decrease) to the pre-charge voltage.When the voltage of the digit line 1010 returns to the pre-chargevoltage, this may cause switching component 1016 to be re-activated,thereby coupling the digit line 1010 with the signal node 1028. Afterswitching component 1016 is reactivated, the polar charge may beintegrated by integrator capacitor 1038 via digit line 1010 and signalnode 1028. After the signal development portion of the read operation,latch 1046 may determine a value stored on memory cell 1004 based on thevoltage of the signal node 1028 and/or on the voltage across integratorcapacitor 1038.

FIG. 11 shows a block diagram 1100 of a memory device that supportstechniques for reading a memory cell using multi-stage memory sensing inaccordance with aspects of the present disclosure. Memory array 100-amay be referred to as an electronic memory apparatus and includes memorycontroller 140-a and memory cell 105-b, which may be examples of memorycontroller 140 and memory cell 105 described with reference to FIG. 1.Memory controller 140-a may include a biasing component 1105 and atiming component 1110 and may operate memory array 100-a as describedwith reference to FIG. 1. Memory controller 140-a may be in electroniccommunication with word line 110-b, digit line 115-b, plate line 210-a,and sense component 125-b, which may be examples of word line 110, digitline 115, plate line 210, and sense component 125 described withreference to FIGS. 1 and 2. Memory array 100-a may also includereference component 1115 and latch 1120. The components of memory array100-a may be in electronic communication with each other and may performthe functions described with reference to FIGS. 1 through 3. In somecases, the sense component 125-b, reference component 1115, and/or thelatch 1120 may be components of memory controller 140-a.

Memory controller 140-a may be configured to assert a signal(s) on oneor more of word line 110-b, plate line 210-a, or digit line 115-b byapplying voltages to those various nodes. For example, the biasingcomponent 1105 may be configured to apply a voltage to operate memorycell 105-b to read or write memory cell 105-b as described above. Insome cases, memory controller 140-a may include a row decoder, columndecoder, or both, as described with reference to FIG. 1. This may enablethe memory controller 140-a to access one or more memory cells 105. Thebiasing component 1105 may also provide voltage potentials to thereference component 1115 in order to generate a reference signal forsense component 125-b. Additionally, the biasing component 1105 mayprovide voltage potentials for the operation of the sense component125-b. In some examples, the memory controller 140-a may control variousphases of a read operation. In some cases, the memory controller 140-amay assert a control signal(s) to activate a transistor(s) to couple anamplifier capacitor with a digit line 115-b. Memory controller 140-a mayalso assert a signal on word line 110-b to couple a memory cell 105-b toa digit line 115-b.

In some cases, the memory controller 140-a may perform its operationsusing the timing component 1110. For example, the timing component 1110may control the timing of the various word line selections, digit lineselections, or plate line biasing, including timing for switching andvoltage application to perform the memory functions, such as reading andwriting, discussed herein. In some cases, the timing component 1110 maycontrol the operations of the biasing component 1105. In some cases, thetiming component 1110 may control the timing of asserting or deassertingcontrol signals (e.g., CS1, CS2) to activate or deactivate one or moreswitching components.

In some cases, the memory array 100-a may include the referencecomponent 1115. The reference component 1115 may include variouscomponents to generate a reference signal for the sense component 125-b.The reference component 1115 may include circuitry configured to producereference signals. In some cases, the reference component 1115 mayinclude other ferroelectric memory cells 105. In some examples, thereference component 1115 may be configured to output a voltage with avalue between the two sense voltages, as described with reference toFIG. 3. Or the reference component 1115 may be designed to output avirtual ground voltage (e.g., approximately 0V).

The sense component 125-b may compare a signal from memory cell 105-b(e.g., through digit line 115-b, as integrated on an integratorcapacitor) with a reference signal (e.g., a reference signal from thereference component 1115). The value may be latched by latch 1120, whereit may be used in accordance with the operations of an electronic deviceof which memory array 100-a is a part. While latch 1120 is depicted asbeing external to sense component 125-b, in some cases, latch 1120 maybe included in sense component 125-b or memory controller 140-a.

In some examples, the sense component may include split capacitors. Insome examples, the sense component may include a variable capacitivecomponent as described with respect to FIGS. 4-9. In some examples, thesense component may include a displacement capacitor and an integratorcapacitor as described with respect to FIG. 10.

FIG. 12 shows a flowchart illustrating a method 1200 that supportssystem level timing budget improvements in accordance with aspects ofthe present disclosure. The operations of method 1200 may be implementedby a memory system (e.g., memory system 1000) or its components asdescribed herein. For example, some operations of method 1200 may beperformed by a memory controller (e.g., memory controller 140) asdescribed with reference to FIGS. 1 and 11. In some examples, aprocessor may execute a set of instructions to control the functionalelements of the memory controller or other aspects of a memory device orsystem that includes the memory device to perform some of the functionsdescribed below. Additionally or alternatively, a memory system mayperform aspects of the functions described below using special-purposehardware.

At 1205, the method may include coupling, during a read operation of amemory cell, a first capacitor (e.g., boost capacitor 434, 834) with avoltage source (e.g., voltage source 426, 826) and a signal node (e.g.,signal node 428), the first capacitor in parallel with a secondcapacitor (e.g., integrator capacitor 438, 838). In some examples, whenthe first capacitor is coupled with the voltage source and the signalnode, it is coupled in parallel with the second capacitor. In someexamples, the first capacitor may be coupled with the voltage source andthe signal node by activating a switching component (e.g., switchingcomponent 432, 832, 848). In some examples, the switching component maybe activated by activating a control signal (e.g., CS1). In someexamples, aspects of the operations of 1205 may be performed asdescribed with reference to FIGS. 1-9.

At 1210, the method may include coupling the memory cell with a digitline (e.g., digit line 115, 410) while the signal node is coupled withthe digit line. In some examples, the memory cell may be coupled withthe digit line by activating a word line signal (WL) on a word line(e.g., word line 110, 402) associated with the memory cell. In someexamples, aspects of the operations of 1210 may be performed asdescribed with reference to FIGS. 1-9.

At 1215, the method may include decoupling the first capacitor from thesignal node or the voltage source after coupling the memory cell withthe digit line. In some examples, the first capacitor may be decoupledfrom the signal node or the voltage source by deactivating a switchingcomponent (e.g., switching component 432, 832, 848). In some examples,aspects of the operations of 1210 may be performed as described withreference to FIGS. 1-9.

At 1220, the method may include determining, after decoupling the firstcapacitor, a value stored on the memory cell based at least in part on avoltage across the second capacitor. In some examples, the value storedon the memory cell may be determined by a latch (e.g., latch 446, 1120).In some examples, aspects of the operations of 1220 may be performed asdescribed with reference to FIGS. 1-9.

In some examples, an apparatus may perform a method or methods asdescribed herein, such as the method 1200, using general- orspecial-purpose hardware. The apparatus may include features, means, orinstructions for coupling, during a read operation of a memory cell, afirst capacitor with a voltage source and a signal node, the firstcapacitor in parallel with a second capacitor; coupling the memory cellwith a digit line while the signal node is coupled with the digit line;decoupling the first capacitor from the signal node or the voltagesource after coupling the memory cell with the digit line; anddetermining, after decoupling the first capacitor, a value stored on thememory cell based at least in part on a voltage across the secondcapacitor. In some examples, coupling the first capacitor comprisesactivating a first switching component to couple the first capacitorwith the voltage source or the signal node. In some examples, decouplingthe first capacitor occurs based at least in part on a fixed delay aftercoupling the memory cell with the digit line. In some examples,decoupling the first capacitor occurs based at least in part on anamount of charge accumulated on the first capacitor. In some examples,decoupling the first capacitor occurs based at least in part on thefirst capacitor becoming fully discharged. In some examples, a node ofthe second capacitor is coupled with the signal node and coupling thememory cell with the digit line causes charge transfer between thesecond capacitor and the memory cell. In some examples, the secondcapacitor has a lower capacitance than the first capacitor. In someexamples, the second capacitor is a non-linear capacitor.

Some examples of the method 1200 and apparatuses described herein mayfurther include processes, features, means, or instructions foractivating a second switching component to couple the second capacitorwith the voltage source or the signal node.

Some examples of the method 1200 and apparatuses described herein mayfurther include processes, features, means, or instructions forincreasing a voltage of the voltage source to increase a voltage of thesignal node via the first capacitor before coupling the memory cell withthe digit line.

Some examples of the method 1200 and apparatuses described herein mayfurther include processes, features, means, or instructions fordecreasing a voltage of the voltage source to decrease a voltage of thesignal node via the second capacitor before determining the value.

FIG. 13 shows a flowchart illustrating a method 1300 that supportssystem level timing budget improvements in accordance with aspects ofthe present disclosure. The operations of method 1300 may be implementedby a memory system (e.g., memory system 1000) or its components asdescribed herein. For example, some operations of method 1300 may beperformed by a memory controller (e.g., memory controller 140) asdescribed with reference to FIGS. 1-2. In some examples, a processor mayexecute a set of instructions to control the functional elements of thememory controller or other aspects of a memory device or system thatincludes the memory device to perform some of the functions describedbelow. Additionally or alternatively, a memory system may performaspects of the functions described below using special-purpose hardware.

At 1305, the method may include coupling, during a read operation of amemory cell, a first capacitor (e.g., boost capacitor 434 with a voltagesource (e.g., voltage source 426) and a signal node (e.g., signal node428), the first capacitor in parallel with a second capacitor (e.g.,integrator capacitor 438). In some examples, when the first capacitor iscoupled with the voltage source and the signal node, it is coupled inparallel with a second capacitor. In some examples, the first capacitormay be coupled with the voltage source and the signal node by activatinga switching component (e.g., switching component 432 or 848). In someexamples, the switching component may be activated by activating acontrol signal (e.g., CS1). In some examples, aspects of the operationsof 1305 may be performed as described with reference to FIGS. 1-9.

At 1310, the method may include coupling the memory cell with a digitline (e.g., digit line 410) while the signal node is coupled with thedigit line. In some examples, the memory cell may be coupled with thedigit line by activating a word line signal (WL) on a word line (e.g.,word line 402) associated with the memory cell. In some examples,coupling the memory cell with the digit line causes charge transferbetween the memory cell and the first capacitor. In some cases, thetransferred charge may be some or all of the displacement charge. Insome examples, aspects of the operations of 1310 may be performed asdescribed with reference to FIGS. 1-9.

At 1315, the method may include decoupling the first capacitor from thesignal node or the voltage source after coupling the memory cell withthe digit line. In some examples, the first capacitor may be decoupledfrom the signal node by deactivating a switching component (e.g.,switching component 432 or switching component 736). In some examples,aspects of the operations of 1315 may be performed as described withreference to FIGS. 1-9.

At 1320, the method may include coupling, after decoupling the firstcapacitor, a second capacitor (e.g., integrator capacitor 438) with thevoltage source and the signal node to transfer charge between the memorycell and the second capacitor. In some cases, the transferred charge maybe some or all of the polar charge. In some cases, the transferredcharge may include a portion of the displacement charge. In someexamples, aspects of the operations of 1320 may be performed asdescribed with reference to FIGS. 1-9.

At 1325, the method may include determining, after coupling the secondcapacitor, a value stored on the memory cell based at least in part on avoltage at the signal node. In some cases, the value may be determinedby a latch (e.g., latch 446, 1120). In some examples, aspects of theoperations of 1325 may be performed as described with reference to FIGS.1-9.

In some examples, an apparatus may perform a method or methods asdescribed herein, such as the method 1300, using general- orspecial-purpose hardware. The apparatus may include features, means, orinstructions for coupling, during a read operation of a memory cell, afirst capacitor with a voltage source and a signal node; coupling thememory cell with a digit line while the digit line is coupled with thesignal node; decoupling, after coupling the memory cell, the firstcapacitor from at least one of the signal node or the voltage source;coupling, after decoupling the first capacitor, a second capacitor withthe voltage source and the signal node to transfer charge between thememory cell and the second capacitor; and determining, after couplingthe second capacitor, a value stored on the memory cell based at leastin part on a voltage at the signal node. In some examples, coupling thefirst capacitor includes activating a first switching component tocouple the first capacitor with the voltage source or the signal node.In some examples, coupling the second capacitor includes activating asecond switching component to couple the second capacitor with thevoltage source or the signal node. In some examples, the first capacitoris decoupled based at least in part on a comparison of a voltage at anode of the first capacitor and a voltage of the digit line. In someexamples, the second capacitor is coupled based at least in part on afixed time delay after the first capacitor is decoupled. In someexamples, the node of the second capacitor is coupled with the signalnode, and wherein the voltage of the signal node depends at least inpart on an amount of charge transferred between the memory cell and thesecond capacitor.

Some examples of the method 1300 and apparatuses described herein mayfurther include processes, features, means, or instructions forincreasing a voltage of the voltage source to increase a voltage of thesignal node via the first capacitor before coupling the memory cell withthe digit line.

FIG. 14 shows a flowchart illustrating a method 1400 that supportssystem level timing budget improvements in accordance with aspects ofthe present disclosure. The operations of method 1400 may be implementedby a memory system (e.g., memory system 1000) or its components asdescribed herein. For example, some operations of method 1400 may beperformed by a memory controller (e.g., memory controller 140) asdescribed with reference to FIGS. 1-2. In some examples, a processor mayexecute a set of instructions to control the functional elements of thememory controller or other aspects of a memory device or system thatincludes the memory device to perform some of the functions describedbelow. Additionally or alternatively, a memory system may performaspects of the functions described below using special-purpose hardware.

At 1405, the method may include pre-charging, during a read operation ofa memory cell (e.g., memory cell 1004), a digit line (e.g., digit line1010) associated with the memory cell while the digit line is coupledwith a signal node (e.g., signal node 1028). In some examples,pre-charging the digit line includes coupling a pre-charge voltagesource (e.g., pre-charge voltage source 1020) with the digit line. Insome examples, pre-charging the digit line includes pre-charging a firstcapacitor (e.g., displacement capacitor 1052) that is coupled with thedigit line. In some examples, aspects of the operations of 1405 may beperformed as described with reference to FIG. 10.

At 1410, the method may include coupling the memory cell with the digitline to cause charge transfer (e.g., a transfer of some or all of thedisplacement charge) between the memory cell and the first capacitorthat is coupled with the digit line. In some cases, charge may betransferred from the first capacitor to the memory cell. In some cases,charge may be transferred from the memory cell to the first capacitor.In some examples the memory cell is coupled with the digit line byactivating a word line signal (WL) on a word line (e.g., word line 1002)associated with the memory cell. In some examples, aspects of theoperations of 1410 may be performed as described with reference to FIG.10.

At 1415, the method may include adjusting a voltage of a voltage source(e.g., voltage source 1026) that is coupled with the first capacitor andwith a second capacitor (e.g., integrator capacitor 1038) that iscoupled with the signal node, wherein adjusting the voltage of thevoltage source decouples the digit line from the signal node. In someexamples, adjusting the voltage source includes increasing the voltageof the voltage source. In some examples, increasing the voltage of thevoltage source increases the voltage of the digit line via the firstcapacitor, which decouples the digit line from the signal node bydeactivating a switching component (e.g., switching component 1016). Insome examples, aspects of the operations of 1415 may be performed asdescribed with reference to FIG. 10.

At 1420, the method may include determining, after adjusting the voltageof the voltage source, a value of the memory cell based at least in parton a voltage of the signal node. In some examples, the value of thememory cell is determined by a latch (e.g., latch 1046, 1120). In someexamples, aspects of the operations of 1420 may be performed asdescribed with reference to FIG. 10.

In some examples, an apparatus may perform a method or methods asdescribed herein, such as the method 1400, using general- orspecial-purpose hardware. The apparatus may include features, means, orinstructions for pre-charging, during a read operation of a memory cell,a digit line associated with the memory cell while the digit line iscoupled with a signal node; coupling the memory cell with the digit lineto cause charge transfer between the memory cell and a first capacitorthat is coupled with the digit line; adjusting a voltage of a voltagesource that is coupled with the first capacitor and with a secondcapacitor that is coupled with the signal node. In some cases, adjustingthe voltage of the voltage source decouples the digit line from thesignal node. The method may further include determining, after adjustingthe voltage of the voltage source, a value of the memory cell based atleast in part on a voltage of the signal node. In some examples,coupling the memory cell with the digit line causes charge transferbetween the memory cell and the second capacitor. In some examples, thevoltage source is a first voltage source and pre-charging the digit lineincludes coupling a second voltage source with the digit line and thefirst capacitor. In some examples, adjusting the voltage of the digitline decouples the digit line from the signal node at least in part bycausing a switching component coupled with the digit line to becomedeactivated.

It should be noted that the methods described (e.g., methods 1200, 1300,1400) above describe possible implementations, and that the operationsand the steps may be rearranged or otherwise modified and that otherimplementations are possible. Further, aspects of two or more of themethods may be combined.

In some examples, a memory device may perform aspects of the functionsdescribed herein. The memory device may include a memory cell; a signalnode configured to be selectively coupled with a digit line of a memorycell during a read operation of the memory cell; a capacitive componentcoupled with a voltage source and the signal node, the capacitivecomponent configured to provide a higher capacitance during a firstportion of the read operation and a lower capacitance during a secondportion of the read operation; and a latch coupled with the signal nodeand configured to determine a value stored on the memory cell based atleast in part on a voltage of the signal node after the second portionof the read operation. In some examples, the capacitive componentincludes a first capacitor configured to be selectively coupled with thevoltage source and the signal node; and a second capacitor coupled withthe voltage source and the signal node. The first capacitor isconfigured to be selectively coupled with the voltage source and thesignal node independent of the second capacitor. In some examples, thefirst capacitor and the second capacitor are configured to be coupled inparallel between the voltage source and the signal node during the firstportion of the read operation, and the first capacitor is configured tobe decoupled from the second capacitor during the second portion of theread operation. In some examples, the second capacitor is configured tobe selectively coupled between the voltage source and the signal node.In some examples, coupling the memory cell with the digit line causescharge transfer between the memory cell and the second capacitor via thesignal node. In some examples, the second capacitor has a lowercapacitance than the first capacitor.

Some examples of the memory device further include a controllerconfigured to activate a first switching component to couple, during thefirst portion of the read operation, the first capacitor between thevoltage source and the signal node in parallel with the secondcapacitor; activate a word line signal to couple the memory cell withthe digit line, deactivate the first switching component to decouple,during the second portion of the read operation, the first capacitorfrom the second capacitor; and activate the latch to determine the valuestored on the memory cell after the second portion of the readoperation. In some examples, the controller is configured to increase avoltage of the voltage source to increase the voltage of the signal nodevia the capacitive component before activating the word line signal. Insome examples, coupling the memory cell with the digit line causes asecond amount of charge to be transferred between the memory cell andthe second capacitor.

Some examples of the memory device further include a second switchingcomponent, wherein the second capacitor is configured to be coupled withthe signal node and the voltage source via activation of the secondswitching component, and wherein the controller is further configured toactivate the second switching component before activating the word linesignal.

In some examples, a memory device may perform aspects of the functionsdescribed herein. The memory device may include a memory cell; a digitline associated with the memory cell; a signal node configured to beselectively coupled with the digit line; a first capacitor coupled withthe digit line and a voltage source; a second capacitor coupled with thevoltage source and the signal node, the second capacitor coupled inseries with the first capacitor; and a latch coupled with the signalnode and configured to determine a value stored on the memory cell basedat least in part on a voltage of the signal node.

Some examples of the memory device further include a controllerconfigured to, during a read operation of the memory cell: pre-chargethe digit line; couple the memory cell with the digit line; increase thevoltage of the voltage source to adjust the voltage of the digit linevia the first capacitor, wherein increasing voltage of the voltagesource causes a first amount of charge to be transferred between thememory cell and the first capacitor via the digit line, and causes thedigit line to be decoupled from the signal node; and activate the latchto determine the value of the memory cell.

Some examples of the memory device further include a switching componentconfigured to couple the digit line with the signal node, wherein:increasing the voltage of the voltage source causes the switchingcomponent to be deactivated.

Information and signals described herein may be represented using any ofa variety of different technologies and techniques. For example, data,instructions, commands, information, signals, bits, symbols, and chipsthat may be referenced throughout the above description may berepresented by voltages, currents, electromagnetic waves, magneticfields or particles, optical fields or particles, or any combinationthereof. Some drawings may illustrate signals as a single signal;however, it will be understood by a person of ordinary skill in the artthat the signal may represent a bus of signals, where the bus may have avariety of bit widths.

The terms “electronic communication,” “conductive contact,” “connected,”and “coupled” may refer to a relationship between components thatsupports the flow of electrons between the components. Components areconsidered in electronic communication with (or in conductive contactwith or connected with or coupled with) one another if there is anyconductive path between the components that can, at any time, supportthe flow of electrons between the components. At any given time, theconductive path between components that are in electronic communicationwith each other (or in conductive contact with or connected with orcoupled with) may be an open circuit or a closed circuit based on theoperation of the device that includes the connected components. Theconductive path between connected components may be a direct conductivepath between the components or the conductive path between connectedcomponents may be an indirect conductive path that may includeintermediate components, such as switches, transistors, or othercomponents. In some cases, the flow of electrons between the connectedcomponents may be interrupted for a time, for example, using one or moreintermediate components such as switches or transistors.

The term “coupling” refers to condition of moving from an open-circuitrelationship between components in which electrons are not presentlycapable of flowing between the components over a conductive path to aclosed-circuit relationship between components in which electronic arecapable of flowing between components over the conductive path. When acomponent, such as a controller, couples other components together, thecomponent initiates a change that allows electrons to flow between theother components over a conductive path that previously did not permitelectrons to flow.

As used herein, the term “substantially” means that the modifiedcharacteristic (e.g., a verb or adjective modified by the termsubstantially) need not be absolute but is close enough so as to achievethe advantages of the characteristic.

The devices discussed herein, including a memory array, may be formed ona semiconductor substrate, such as silicon, germanium, silicon-germaniumalloy, gallium arsenide, gallium nitride, etc. In some cases, thesubstrate is a semiconductor wafer. In other cases, the substrate may bea silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG)or silicon-on-sapphire (SOP), or epitaxial layers of semiconductormaterials on another substrate. The conductivity of the substrate, orsub-regions of the substrate, may be controlled through doping usingvarious chemical species including, but not limited to, phosphorous,boron, or arsenic. Doping may be performed during the initial formationor growth of the substrate, by ion-implantation, or by any other dopingmeans.

A switching component or a transistor discussed herein may represent afield-effect transistor (FET) and include a three terminal deviceincluding a source, drain, and gate. The terminals may be connected toother electronic elements through conductive materials, e.g., metals.The source and drain may be conductive and may include a heavily-doped,e.g., degenerate, semiconductor region. The source and drain may beseparated by a lightly-doped semiconductor region or channel. If thechannel is n-type (i.e., majority carriers are electrons), then the FETmay be referred to as a n-type FET. If the channel is p-type (i.e.,majority carriers are holes), then the FET may be referred to as ap-type FET. The channel may be capped by an insulating gate oxide. Thechannel conductivity may be controlled by applying a voltage to thegate. For example, applying a positive voltage or negative voltage to ann-type FET or a p-type FET, respectively, may result in the channelbecoming conductive. A transistor may be “on” or “activated” when avoltage greater than or equal to the transistor's threshold voltage isapplied to the transistor gate. The transistor may be “off” or“deactivated” when a voltage less than the transistor's thresholdvoltage is applied to the transistor gate.

The description set forth herein, in connection with the appendeddrawings, describes example configurations and does not represent allthe examples that may be implemented or that are within the scope of theclaims. The term “exemplary” used herein means “serving as an example,instance, or illustration,” and not “preferred” or “advantageous overother examples.” The detailed description includes specific details forthe purpose of providing an understanding of the described techniques.These techniques, however, may be practiced without these specificdetails. In some instances, well-known structures and devices are shownin block diagram form in order to avoid obscuring the concepts of thedescribed examples.

In the appended figures, similar components or features may have thesame reference label. Further, various components of the same type maybe distinguished by following the reference label by a dash and a secondlabel that distinguishes among the similar components. If just the firstreference label is used in the specification, the description isapplicable to any one of the similar components having the same firstreference label irrespective of the second reference label.

Information and signals described herein may be represented using any ofa variety of different technologies and techniques. For example, data,instructions, commands, information, signals, bits, symbols, and chipsthat may be referenced throughout the above description may berepresented by voltages, currents, electromagnetic waves, magneticfields or particles, optical fields or particles, or any combinationthereof.

The various illustrative blocks and modules described in connection withthe disclosure herein may be implemented or performed with ageneral-purpose processor, a DSP, an ASIC, a field-programmable gatearray (FPGA) or other programmable logic device, discrete gate ortransistor logic, discrete hardware components, or any combinationthereof designed to perform the functions described herein. Ageneral-purpose processor may be a microprocessor, but in thealternative, the processor may be any conventional processor,controller, microcontroller, or state machine. A processor may also beimplemented as a combination of computing devices (e.g., a combinationof a digital signal processor (DSP) and a microprocessor, multiplemicroprocessors, one or more microprocessors in conjunction with a DSPcore, or any other such configuration).

The functions described herein may be implemented in hardware, softwareexecuted by a processor, firmware, or any combination thereof. Ifimplemented in software executed by a processor, the functions may bestored on or transmitted over as one or more instructions or code on acomputer-readable medium. Other examples and implementations are withinthe scope of the disclosure and appended claims. For example, due to thenature of software, functions described above can be implemented usingsoftware executed by a processor, hardware, firmware, hardwiring, orcombinations of any of these. Features implementing functions may alsobe physically located at various positions, including being distributedsuch that portions of functions are implemented at different physicallocations. Also, as used herein, including in the claims, “or” as usedin a list of items (for example, a list of items prefaced by a phrasesuch as “at least one of” or “one or more of”) indicates an inclusivelist such that, for example, a list of at least one of A, B, or C meansA or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, asused herein, the phrase “based on” shall not be construed as a referenceto a closed set of conditions. For example, an exemplary step that isdescribed as “based on condition A” may be based on both a condition Aand a condition B without departing from the scope of the presentdisclosure. In other words, as used herein, the phrase “based on” shallbe construed in the same manner as the phrase “based at least in parton.”

The description herein is provided to enable a person skilled in the artto make or use the disclosure. Various modifications to the disclosurewill be readily apparent to those skilled in the art, and the genericprinciples defined herein may be applied to other variations withoutdeparting from the scope of the disclosure. Thus, the disclosure is notlimited to the examples and designs described herein, but is to beaccorded the broadest scope consistent with the principles and novelfeatures disclosed herein.

1. (canceled)
 2. A method, comprising: coupling, during a read operationof a memory cell, a first capacitor with a voltage source and a node,the first capacitor in parallel with a second capacitor while coupledwith the voltage source and the node; changing, after coupling the firstcapacitor with the voltage source and the node, a voltage of the voltagesource to change a voltage of the node; coupling the memory cell with anaccess line while the node is coupled with the access line; decouplingthe first capacitor from the node or the voltage source after couplingthe memory cell with the access line; and determining, after decouplingthe first capacitor, a value stored on the memory cell based at least inpart on a voltage across the second capacitor.
 3. The method of claim 2,wherein changing the voltage source to change the voltage of the nodecomprises increasing the voltage of the voltage source while the firstcapacitor is coupled with the voltage source and the node.
 4. The methodof claim 3, wherein coupling the memory cell with the access line occursafter increasing the voltage of the voltage source.
 5. The method ofclaim 2, wherein changing the voltage source to change the voltage ofthe node comprises decreasing the voltage of the voltage source afterthe first capacitor is decoupled from the node or the voltage source. 6.The method of claim 5, wherein determining the value stored on thememory cell occurs after decreasing the voltage of the voltage source.7. The method of claim 2, wherein decoupling the first capacitor occursbased at least in part on coupling the memory cell with the access line.8. The method of claim 2, wherein decoupling the first capacitor occursafter coupling the memory cell with the access line.
 9. The method ofclaim 2, wherein decoupling the first capacitor occurs based at least inpart on an amount of charge accumulated on the first capacitor.
 10. Themethod of claim 2, wherein decoupling the first capacitor occurs basedat least in part on discharging the first capacitor.
 11. An apparatus,comprising: a memory cell; a node configured to be selectively coupledwith an access line of the memory cell during a read operation of thememory cell; a capacitive component coupled with a voltage source andthe node, the capacitive component configured to provide a highercapacitance during a first portion of the read operation and a lowercapacitance during a second portion of the read operation; a latchcoupled with the node; and a controller configured to: increase avoltage of the voltage source during the first portion of the readoperation; and activate the latch to determine a value stored on thememory cell after increasing the voltage of the voltage source.
 12. Theapparatus of claim 11, wherein the capacitive component comprises afirst capacitor and a second capacitor, and wherein the controller isfurther configured to: increase the voltage of the voltage source whilethe first capacitor and the second capacitor are coupled with thevoltage source and the node; and decouple the first capacitor from thenode or the voltage source after increasing the voltage of the voltagesource.
 13. The apparatus of claim 12, wherein the controller is furtherconfigured to: decrease the voltage of the voltage source beforeactivating the latch.
 14. The apparatus of claim 12, wherein thecontroller is further configured to: couple the memory cell with theaccess line while the first capacitor is coupled with the voltage sourceand the node.
 15. The apparatus of claim 12, wherein the secondcapacitor is configured to be selectively coupled between the voltagesource and the node.
 16. The apparatus of claim 12, wherein the firstcapacitor has a different capacitance than the second capacitor.
 17. Theapparatus of claim 11, wherein the controller is further configured to:couple the memory cell with the access line after increasing the voltageof the voltage source.
 18. The apparatus of claim 11, wherein the latchis configured to determine the value stored on the memory cell based atleast in part on a voltage of the node.
 19. An apparatus, comprising: amemory cell; a node configured to be selectively coupled with an accessline of the memory cell during a read operation of the memory cell; avoltage source configured to be change voltage during the readoperation; a capacitive component coupled with the node and the voltagesource, the capacitive component configured to have a first capacitanceduring a first portion of the read operation and a second capacitanceduring a second portion of the read operation; and a latch coupled withthe node and configured to determine a value stored on the memory cellbased at least in part on a voltage of the node while the capacitivecomponent has the second capacitance.
 20. The apparatus of claim 19,wherein the capacitive component comprises a first capacitor and asecond capacitor, and wherein the first capacitor is selectively coupledwith the node or the voltage source.
 21. The apparatus of claim 20,wherein the second capacitor is selectively coupled with the node or thevoltage source.